Mitigating Multi-bit Soft Errors in L1 Caches Using Last-Store Prediction

Recent studies suggest that the rate of spatial multi-bit soft errors will increase with future technology scaling. Unfortunately, multi-bit errors cannot be effectively mitigated with conventional techniques in L1 data caches (e.g., bit interleaving or stronger coding) due to high power and/or latency overheads. We propose the laststore predictor, a lightweight prediction mechanism that accurately determines when a cache block is written for the last time and writes the data back to the L2 cache where increased access latency permits more effective multi-bit error protection. Using a combination of commercial workloads and SPEC CPU2000 benchmarks, we show that, on average, write-back L1 data caches are 42% vulnerable to multi-bit soft errors. Where SECDED ECC fails to mitigate multi-bit errors, our mechanism reduces the multi-bit soft-error vulnerability to 12% on average.